Metal oxide metal capacitor with slot vias

ABSTRACT

A capacitor includes the first electrode including the first conductive lines and vias. The first conductive lines on the same layer are parallel to each other and connected to a first periphery conductive line. The first conductor lines are aligned in adjacent layers and are coupled to each other by the vias. The capacitor further includes a second electrode aligned opposite to the first electrode including second conductive lines and vias. The second conductive lines on the same layer are parallel to each other and connected to a second periphery conductive line. The second conductor lines are aligned in adjacent layers and are coupled to each other by the vias. The capacitor further includes oxide layers formed between the first electrode and the second electrode. The vias have rectangular (slot) shapes on a layout. In one embodiment, the conductive lines and vias are metal, e.g. copper, aluminum, or tungsten.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of U.S. Provisional PatentApplication Ser. No. 61/173,439, filed on Apr. 28, 2009, which isincorporated herein by reference in its entirety.

TECHNICAL FIELD

This disclosure relates generally to Metal Oxide Metal (MOM) capacitor,more specifically MOM capacitor with a slot (rectangular) via structure.

BACKGROUND

An exemplary single layer Metal-oxide-metal (MOM) capacitor structure isshown in FIG. 1A. The structure 100 has periphery metal 102, metal lines104, and dielectric (oxide) layers 106. To increase the area usageefficiency, multiple layers of MOM capacitor structures could bevertically stacked together. FIG. 1B illustrates a stack (multi-layer)MOM capacitor structure, using vias 112 to connect each layer.

MOM capacitors have been used in the integrated circuits increasinglymore often, partly because their minimal capacitive loss to thesubstrate results in high quality capacitors. Also, MOM capacitors withvia have low cost and are easy to implement using a standard logicprocess. However, conventional MOM capacitors with via tend to have lowcapacitance and high resistance. Accordingly, important goals inmanufacturing MOM capacitors are to increase the capacitance and reducecapacitor resistance, especially for Mixed Signal Radio Frequency (MSRF)product applications. Further, via resistance uniformity and reliableperformance are important issues for MOM capacitors with high viadensity.

Accordingly, new structures and methods for MOM capacitors are desiredto achieve higher capacitance and lower resistance, as well asperformance reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1A illustrates an exemplary single layer Metal-oxide-metal (MOM)capacitor structure;

FIG. 1B illustrates a stack (multi-layer) MOM capacitor structure, usingvias to connect each layer;

FIG. 2A illustrates a top view of an example of a conventionalmulti-layer MOM capacitor structure with vias shown in dotted linesunderneath the metal lines;

FIG. 2B illustrates a partial side view of a conventional multi-layerMOM capacitor structure with vias between two metal layers;

FIG. 2C illustrates a top view of an example of another conventionalmulti-layer MOM capacitor structure with vias shown in dotted linesunderneath the metal lines;

FIG. 3A illustrates a top view of an exemplary multi-layer MOM capacitorstructure according to one aspect of this disclosure with vias shown indotted lines underneath the metal lines;

FIG. 3B illustrates a partial side view of an exemplary multi-layer MOMcapacitor structure according to one aspect of this disclosure with viasbetween two metal layers;

FIG. 4A-FIG. 4C illustrate a top view of other embodiments of amulti-layer MOM capacitor structure according to one aspect of thisdisclosure with vias shown in dotted lines underneath the metal lines;and

FIG. 5A-FIG. 5B illustrate a top view of different embodiments of amulti-layer MOM capacitor structure according to another aspect of thisdisclosure with vias shown in dotted lines underneath the metal lines.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent disclosure provides many applicable novel concepts that can beembodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative and do not limit the scopeof the disclosure.

A novel structure for Metal-oxide-metal (MOM) capacitor with slot(rectangular) vias is provided. The structure uses slot (rectangular)vias to lower resistance and increase capacitance due to extended vialength and increased sidewall area. Throughout the various views andillustrative embodiments of the present disclosure, like referencenumbers are used to designate like elements.

FIG. 2A illustrates a top view of an example of a conventionalmulti-layer MOM capacitor structure 200 with vias shown in dotted linesunderneath the metal lines. The structure 200 has periphery metal 102,metal lines 104, and dielectric (oxide) layers 106. The vias 112 aresquare vias with a fixed size depending on the process (e.g. 0.05μm×0.05 μm in a 32 nm process). The vias 112 are aligned with each otheracross multiple metal lines 104 from the top-view shown in FIG. 2A. Thevias 112 connect each metal layer of the multi-layer MOM structure 200.

FIG. 2B illustrates a partial side view of a conventional multi-layerMOM capacitor structure with vias between two metal layers. The vias 112connect metal lines 104 on different layers.

FIG. 2C illustrates a top view of an example of another conventionalmulti-layer MOM capacitor structure with vias shown in dotted linesunderneath the metal lines. The structure 220 has periphery metal 102,metal lines 104, and dielectric (oxide) layers 106. The vias 112 aresquare vias with a fixed size depending on the process. The vias 112 arestaggered across multiple metal lines 104 from the top-view shown inFIG. 2C. Even though the layout of the structure 220 is different fromthat of the structure 200, they both use fixed size square vias 112 toconnect metal lines 104 between each layer.

FIG. 3A illustrates a top view of an exemplary multi-layer MOM capacitorstructure according to one aspect of this disclosure with vias shown indotted lines underneath the metal lines. The structure 300 has peripherymetal 102, metal lines 104, and dielectric (oxide) layers 106. Theperiphery metal 102 and metal lines 104 could be copper, aluminum,tungsten, etc. The vias 302 are slot (rectangular) vias with a variablesize depending on the process (e.g., 0.05 μm×0.13 μm in a 32 nmprocess). The vias 302 are aligned with each other across multiple metallines 104 from the top-view shown in FIG. 3A. The vias 112 connect eachmetal layer of the multi-layer MOM structure 300. MOM capacitor withslot via structure can increase capacitance and reduce resistance byextended via length and increased via sidewall area.

In one embodiment of the structure 300 using the slot vias 302 with thesize of 0.05 μm×0.13 μm, the capacitance increased about 1.6 times(10.34 pF), compared to one embodiment of the structure 200 using squarevias 112 with the size of 0.05 μm×0.05 μm (6.477 pF). This capacitanceincrease is due to extended via length and increased sidewall area fromusing slot (rectangular) 302 instead of square vias 112.

FIG. 3B illustrates a partial side view of an exemplary multi-layer MOMcapacitor structure according to one aspect of this disclosure with viasbetween two metal layers. The vias 302 connect metal lines 104 ondifferent layers.

FIG. 4A-FIG. 4C illustrate a top view of other embodiments of amulti-layer MOM capacitor structure according to one aspect of thisdisclosure with vias shown in dotted lines underneath the metal lines.In FIG. 4A, the structure 400 has periphery metal 102, metal lines 104,and dielectric (oxide) layers 106. The vias 302 are slot (rectangular)vias with a variable size depending on the process (e.g., 0.05 μm×0.13μm). The vias 302 are staggered across multiple metal lines 104 in they-direction from the top-view shown in FIG. 4A. Even though the layoutof the structure 400 is different from that of the structure 300, theyboth use slot vias 302 to connect metal lines 104 between each layer.

In FIG. 4B, the structure 410 has periphery metal 102, metal lines 104,and dielectric (oxide) layers 106. The vias 302 are slot (rectangular)vias with a variable size depending on the process (e.g., 0.05 μm×0.13μm). The vias 402 are square vias with a variable size depending on theprocess (e.g. 0.05 μm×0.05 μm). In the structure 410, the vias 302 and402 are used together (each on separate metal lines 104) and staggeredacross multiple metal lines 104 from the top-view shown in FIG. 4B. Inanother embodiment, the vias 302 and 402 can be mixed together in thesame metal lines 104.

In FIG. 4C, the structure 420 has periphery metal 102, metal lines 104,and dielectric (oxide) layers 106. Like the structure 410, the vias 302and 402 are used together (each on separate metal lines 104) in thestructure 420, but the vias 302 and 402 are aligned with each otheracross multiple metal lines 104 from the top-view shown in FIG. 4C. Inanother embodiment, the vias 302 and 402 can be mixed together in thesame metal lines 104.

FIG. 5A-FIG. 5B illustrate a top view of different embodiments of amulti-layer MOM capacitor structure according to another aspect of thisdisclosure with vias shown in dotted lines underneath the metal lines.In FIG. 5A, the structure 500 has periphery metal 102, metal lines 104,and dielectric (oxide) layers 106. The vias 302 are slot (rectangular)vias with a variable size depending on the process (e.g., 0.05 μm×0.13μm). The vias 502 are different size (elongated) rectangular vias. Thevias 302 and 502 are alternating on different metal lines 104. The vias302 are aligned with each other across multiple metal lines 104 from thetop-view shown in FIG. 5A.

In FIG. 5B, the structure 510 has periphery metal 102, metal lines 104,and dielectric (oxide) layers 106. The vias 402 are square vias with avariable size depending on the process (e.g. 0.05 μm×0.05 μm). The vias502 are elongated rectangular vias with a variable size depending on theprocess. The vias 402 and 502 are alternating on different metal lines104. The vias 402 are aligned with each other across multiple metallines 104 from the top-view shown in FIG. 5B.

The advantages of the new structures include increased capacitance andreduced resistance due to extended via lengths and increased viasidewall area. A skilled person in the art will appreciate that therecan be many embodiment variations of this disclosure. For example,instead of slot (rectangular) vias, vias with other shapes (e.g.circular, oval, etc.) could be used, and many different size vias couldbe mixed and arranged in the structures for different embodiments.

Although the present disclosure and its advantages have been describedin detail, it should be understood that various changes, substitutionsand alterations can be made herein without departing from the spirit andscope of the disclosure. Moreover, the scope of the present applicationis not intended to be limited to the particular embodiments of theprocess, machine, manufacture, and composition of matter, means, methodsand steps described in the specification. As one of ordinary skill inthe art will readily appreciate from the disclosure, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized.

1. A capacitor comprising: a first electrode comprising a plurality offirst conductive lines and vias, wherein the first conductive lines onthe same layer are parallel to each other and connected to a firstperiphery conductive line, and the first conductor lines aligned inadjacent layers are coupled to each other by the vias, wherein the viasconnected to the first conductive lines have a first length parallel tothe first conductive lines; a second electrode aligned opposite to thefirst electrode comprising a plurality of second conductive lines andvias, wherein the second conductive lines on the same layer are parallelto each other and connected to a second periphery conductive line, andthe second conductor lines aligned in adjacent layers are coupled toeach other by the vias, wherein the vias connected to the secondconductive lines have a second length parallel to the second conductivelines and different than the first length; and oxide layers formedbetween the first electrode and the second electrode, wherein the viashave rectangular shape on a layout.
 2. The capacitor of claim 1, whereinthe first conductive lines and the second conductive lines are metal. 3.The capacitor of claim 2, wherein the first conductive lines and thesecond conductive lines are copper, aluminum, or tungsten.
 4. Thecapacitor of claim 1, wherein the vias are metal.
 5. The capacitor ofclaim 4, wherein the vias are copper, aluminum, or tungsten.
 6. Thecapacitor of claim 1, wherein the vias are aligned with each otheracross the first conductive lines and the second conductive lines on thesame layer.
 7. The capacitor of claim 1, wherein the vias are staggeredacross the first conductive lines and the second conductive lines on thesame layer.
 8. The capacitor of claim 1, wherein the vias haverectangular shape of various sizes.
 9. The capacitor of claim 1, whereinthe vias have both rectangular and square shapes.
 10. The capacitor ofclaim 9, wherein the vias coupling the first conductive lines arerectangular while the vias coupling the second conductive lines aresquare.
 11. A capacitor comprising: a first electrode comprising aplurality of first metal lines and vias, wherein the first metal lineson the same layer are parallel to each other and connected to a firstperiphery metal line, and the first metal lines aligned in adjacentlayers are coupled to each other by the vias, wherein at least one firstvia connected to the first conductive lines has a first length parallelto the first conductive lines, at least one second via connected to thefirst conductive lines has a second length parallel to the firstconductive line, and the first length is different from the secondlength; a second electrode aligned opposite to the first electrodecomprising a plurality of second metal lines and vias, wherein thesecond metal lines on the same layer are parallel to each other andconnected to a second periphery metal line, and the second metal linesaligned in adjacent layers are coupled to each other by the vias,wherein at least one third via connected to the second conductive lineshas a third length parallel to the second conductive lines and the thirdlength is equal to one of the first length or second length; and oxidelayers formed between the first electrode and the second electrode,wherein the vias have rectangular shape on a layout.
 12. The capacitorof claim 11, wherein the first metal lines, the second metal lines, andvias are copper, aluminum, or tungsten.
 13. The capacitor of claim 11,wherein the vias are aligned with each other across the first metallines and the second metal lines on the same layer.
 14. The capacitor ofclaim 13, wherein the vias are staggered across the first metal linesand the second metal lines on the same layer.
 15. The capacitor of claim11, wherein the vias have rectangular shape of various sizes.
 16. Thecapacitor of claim 11, wherein the vias have both rectangular and squareshapes.
 17. The capacitor of claim 11, wherein at least one fourth viaconnected to the second conductive lines has a fourth length parallel tothe second conductive lines and the fourth length is different than thethird length.
 18. A capacitor comprising: a first electrode comprising aplurality of first metal lines and vias, wherein the first metal lineson the same layer are parallel to each other and connected to a firstperiphery metal line, and the first metal lines aligned in adjacentlayers are coupled to each other by the vias, wherein the vias connectedto the first metal lines have a first length parallel to the first metallines; a second electrode aligned opposite to the first electrodecomprising a plurality of second metal lines and vias, wherein thesecond metal lines on the same layer are parallel to each other andconnected to a second periphery metal line, and the second metal linesaligned in adjacent layers are coupled to each other by the vias,wherein the vias connected to the second conductive lines have a secondlength parallel to the second conductive lines and different than thefirst length; and oxide layers formed between the first electrode andthe second electrode, wherein the first metal lines, the second metallines, and vias are copper, aluminum, or tungsten, and the vias haverectangular shape on a layout.
 19. The capacitor of claim 18, whereinthe vias have rectangular shape of various sizes.
 20. The capacitor ofclaim 18, wherein the vias have both rectangular and square shapes.